As the integration density of semiconductor memories, for example synchronous DRAMs, SDRAMs or DDR-DRAMs, has increased, greater requirements have been made of a data transmission rate when transmitting data streams from external circuit units to a memory cell array of a semiconductor memory. In principle two measures can be taken to increase a data transmission rate.
(i) A width of a chip-internal data bus is increased or a width of internal data transmission paths is increased; and
(ii) A clock frequency is increased.
Generally, a data transmission rate is calculated per connecting unit (or pin) in megabits per second (Mbit/s per connecting unit). For example, a conventional personal computer device under the designation PC100 has a data transmission rate of 100 Mbit/s per connecting unit (pin), it being possible to make available 1600 Mbit/s per PC100 device with a customarily provided arrangement of 16 connecting units (pins).
It is thus possible to detect that a data transmission rate increases proportionally to an increase in a number of connecting units. However, for reasons of fabrication technology and for reasons of the handling capabilities of PC devices, the maximum number of connecting units is limited, as a result of which an increase in a data transmission rate is limited by making data transmission paths wider.
Furthermore, with conventional arrangements the clock frequency which determines the data transmission rate is disadvantageously limited. Striking a balance between the clock frequency and a bus width or a width of data transmission paths leads to a situation in which each connecting unit (pin) of a PC device has to be utilized to an optimum degree or as effectively as possible.
FIG. 3 shows a conventional circuit arrangement for transmitting data between an (external) circuit unit (103) and a memory cell array (102). A 16-bit-wide data transmission path connects the external circuit unit (103) to a storage data stream connecting unit 300a, which in turn transmits a storage data stream 303 to a storage data stream receiver 304 via a data transmission path which is also 16 bits wide. At the same time, i.e. parallel to the transmission described above, a 1-bit-wide mask data stream 305 is transmitted to a mask data stream connecting unit 300 and from there on to a mask data stream receiver 302, also via a 1-bit-wide data transmission path.
The mask data stream 305 is supplied to two mask register components 301a, 301b of a mask register 301 which is located within a register unit 115. The storage data stream 303 is fed via a 16-bit-wide data transmission path to data register components 108a, 108b which are arranged in a data register 108 which forms the other part of the register unit 115.
It is thus a disadvantage of conventional circuit arrangements for transmitting data into a memory cell array 102 that an additional connecting unit 300 has to be made available for the transmission of the mask data stream 305. It is in particular inexpedient to make available a 1-bit-wide data transmission path for the mask data stream 305 which only contains information on which data of the storage data stream 303 are to be ultimately transmitted to the memory cell array 102.